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Structure and role of the processor and its components: AQA A‑Level Computer Science questions

Every AQA A-Level Computer Science exam question on 4.7.3 Structure and role of the processor and its components, 2020–2025, with its mark scheme and examiner’s report.

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561 questions

  1. Q07.2

    June 2025 · Paper 2

    The whole paper ↗
    June 2025 Paper 2, question 07.2: Describe the roles of the following three components of a processor. [6 marks] Control unit General purpose registers Status register
  2. Q07.3

    June 2025 · Paper 2

    The whole paper ↗
    June 2025 Paper 2, question 07.3: All of the processor’s general purpose registers can be referenced using each of the operands in the ADD instruction in Figure 3. Calculate the maximum number o
  3. Q14

    June 2025 · Paper 2

    The whole paper ↗
    June 2025 Paper 2, question 14: An assembly language program is used to control the operation of a robot. The program uses the AQA assembly language instruction set in Table 3 on page 36. The
  4. Q09.1

    June 2025 · AS Paper 2

    The whole paper ↗
    June 2025 AS Paper 2, question 09.1: Describe the roles of the memory address register (MAR) and memory buffer register (MBR) in the fetch stage of the Fetch-Execute cycle. [2 marks] MAR MBR
  5. Q09.2

    June 2025 · AS Paper 2

    The whole paper ↗
    June 2025 AS Paper 2, question 09.2: Describe what happens during the decode stage of the Fetch-Execute cycle, including the role of any dedicated registers. [3 marks]
  6. Q10.1

    June 2025 · AS Paper 2

    The whole paper ↗
    June 2025 AS Paper 2, question 10.1: Table 1 shows the standard AQA assembly language instruction set that should be used to answer question . 1 1 0 and question 1 0 . 2 Table 1 – standard AQA asse
  7. Q10.2

    June 2025 · AS Paper 2

    The whole paper ↗
    June 2025 AS Paper 2, question 10.2: Triangular numbers are numbers that count the number of objects that would appear when arranged in an equilateral triangle. The sequence of triangular numbers s
  8. Q10.1

    June 2024 · Paper 2

    The whole paper ↗
    June 2024 Paper 2, question 10.1: Complete the trace table below to show the results of executing the program in Figure 7 when the initial value in memory location 130 is 83 Each register can ho
  9. June 2024 Paper 2, question 10.2: The value in memory location 130 before the program is executed is the program’s input and the value stored in memory location 130 when the program finishes exe
  10. Q07.1

    June 2024 · AS Paper 2

    The whole paper ↗
    June 2024 AS Paper 2, question 07.1: Figure 5 shows some of the processor registers and buses that are used during the fetch stage of the fetch-execute cycle, together with the main memory. Figure
  11. Q07.3

    June 2024 · AS Paper 2

    The whole paper ↗
    June 2024 AS Paper 2, question 07.3: In a particular processor instruction set, each instruction consists of an opcode and an operand. An operand could be an immediate value to be used by a program
  12. Q07.4

    June 2024 · AS Paper 2

    The whole paper ↗
    June 2024 AS Paper 2, question 07.4: Computer A and Computer B both have a processor with a clock speed of 2.8 GHz but Computer A performs tasks much faster than Computer B. Computer A has a larger
  13. Q08

    June 2024 · AS Paper 2

    The whole paper ↗
    June 2024 AS Paper 2, question 08: Table 1 – standard AQA assembly language instruction set LDR Rd, <memory ref> Load the value stored in the memory location specified by <memory ref> into regist
  14. Q04.1

    June 2023 · Paper 2

    The whole paper ↗
    June 2023 Paper 2, question 04.1: Describe how the fetch-execute cycle is used to carry out machine code instructions and how the hardware of a computer could be improved so that programs can be
  15. Q04.2

    June 2023 · Paper 2

    The whole paper ↗
    June 2023 Paper 2, question 04.2: An interrupt may occur during the fetch-execute cycle. Describe what an interrupt is and explain the purpose of interrupts. [2 marks]
  16. Q07.1

    June 2023 · Paper 2

    The whole paper ↗
    June 2023 Paper 2, question 07.1: and 07.2 you should assume that memory locations and registers store 8-bit values. These question parts use the AQA assembly language instruction set in Table 3
  17. Q07.2

    June 2023 · Paper 2

    The whole paper ↗
    June 2023 Paper 2, question 07.2: you should assume that memory locations and registers store 8-bit values. These question parts use the AQA assembly language instruction set in Table 3 on page
  18. Q07.3

    June 2023 · Paper 2

    The whole paper ↗
    June 2023 Paper 2, question 07.3: A computer program is required to display the value of the contents of a memory location that stores an 8-bit value. The value should be displayed on the screen
  19. Q08.1

    June 2023 · AS Paper 2

    The whole paper ↗
    June 2023 AS Paper 2, question 08.1: Explain the role of the status register in a processor and describe a circumstance that would result in its contents being updated. [2 marks]
  20. Q08.3

    June 2023 · AS Paper 2

    The whole paper ↗
    June 2023 AS Paper 2, question 08.3: Alice compiles a program on her computer to produce an executable file. Alice can run the executable file on her computer. Bob’s computer has a different proces
All 44 questions on Structure and role of the processor and its components, as a list
  1. June 2025, Paper 2, Q07.2 (6 marks): Describe the roles of the following three components of a processor. [6 marks] Control unit General purpose registers Status register
  2. June 2025, Paper 2, Q07.3 (1 mark): All of the processor’s general purpose registers can be referenced using each of the operands in the ADD instruction in Figure 3. Calculate the maximum number o
  3. June 2025, Paper 2, Q14 (6 marks): An assembly language program is used to control the operation of a robot. The program uses the AQA assembly language instruction set in Table 3 on page 36. The
  4. June 2025, AS Paper 2, Q09.1 (2 marks): Describe the roles of the memory address register (MAR) and memory buffer register (MBR) in the fetch stage of the Fetch-Execute cycle. [2 marks] MAR MBR
  5. June 2025, AS Paper 2, Q09.2 (3 marks): Describe what happens during the decode stage of the Fetch-Execute cycle, including the role of any dedicated registers. [3 marks]
  6. June 2025, AS Paper 2, Q10.1 (1 mark): Table 1 shows the standard AQA assembly language instruction set that should be used to answer question . 1 1 0 and question 1 0 . 2 Table 1 – standard AQA asse
  7. June 2025, AS Paper 2, Q10.2 (4 marks): Triangular numbers are numbers that count the number of objects that would appear when arranged in an equilateral triangle. The sequence of triangular numbers s
  8. June 2024, Paper 2, Q10.1 (6 marks): Complete the trace table below to show the results of executing the program in Figure 7 when the initial value in memory location 130 is 83 Each register can ho
  9. June 2024, Paper 2, Q10.2 (2 marks): The value in memory location 130 before the program is executed is the program’s input and the value stored in memory location 130 when the program finishes exe
  10. June 2024, AS Paper 2, Q07.1 (2 marks): Figure 5 shows some of the processor registers and buses that are used during the fetch stage of the fetch-execute cycle, together with the main memory. Figure
  11. June 2024, AS Paper 2, Q07.3 (2 marks): In a particular processor instruction set, each instruction consists of an opcode and an operand. An operand could be an immediate value to be used by a program
  12. June 2024, AS Paper 2, Q07.4 (2 marks): Computer A and Computer B both have a processor with a clock speed of 2.8 GHz but Computer A performs tasks much faster than Computer B. Computer A has a larger
  13. June 2024, AS Paper 2, Q08 (4 marks): Table 1 – standard AQA assembly language instruction set LDR Rd, <memory ref> Load the value stored in the memory location specified by <memory ref> into regist
  14. June 2023, Paper 2, Q04.1 (12 marks): Describe how the fetch-execute cycle is used to carry out machine code instructions and how the hardware of a computer could be improved so that programs can be
  15. June 2023, Paper 2, Q04.2 (2 marks): An interrupt may occur during the fetch-execute cycle. Describe what an interrupt is and explain the purpose of interrupts. [2 marks]
  16. June 2023, Paper 2, Q07.1 (1 mark): and 07.2 you should assume that memory locations and registers store 8-bit values. These question parts use the AQA assembly language instruction set in Table 3
  17. June 2023, Paper 2, Q07.2 (1 mark): you should assume that memory locations and registers store 8-bit values. These question parts use the AQA assembly language instruction set in Table 3 on page
  18. June 2023, Paper 2, Q07.3 (10 marks): A computer program is required to display the value of the contents of a memory location that stores an 8-bit value. The value should be displayed on the screen
  19. June 2023, AS Paper 2, Q08.1 (2 marks): Explain the role of the status register in a processor and describe a circumstance that would result in its contents being updated. [2 marks]
  20. June 2023, AS Paper 2, Q08.3 (2 marks): Alice compiles a program on her computer to produce an executable file. Alice can run the executable file on her computer. Bob’s computer has a different proces
  21. June 2023, AS Paper 2, Q09 (4 marks): Table 2 – standard AQA assembly language instruction set LDR Rd, <memory ref> Load the value stored in the memory location specified by <memory ref> into regist
  22. June 2023, AS Paper 2, Q10 (2 marks): A company is redesigning the processor used in a smartwatch it sells. The redesign will allow the company to increase the clock speed of the processor. The proc
  23. June 2022, Paper 2, Q09.1 (1 mark): LDR Rd, <memory ref> Load the value stored in the memory location specified by <memory ref> into register d. STR Rd, <memory ref> Store the value that is in reg
  24. June 2022, Paper 2, Q09.2 (5 marks): LDR Rd, <memory ref> Load the value stored in the memory location specified by <memory ref> into register d. STR Rd, <memory ref> Store the value that is in reg
  25. June 2022, Paper 2, Q09.3 (1 mark): LDR Rd, <memory ref> Load the value stored in the memory location specified by <memory ref> into register d. STR Rd, <memory ref> Store the value that is in reg
  26. June 2022, AS Paper 2, Q08.1 (3 marks): The fetch-execute cycle involves the Current Instruction Register (CIR), Control Unit, Memory Address Register (MAR), Memory Buffer Register (MBR) and Program C
  27. June 2022, AS Paper 2, Q08.3 (1 mark): State the name of the processor component that is responsible for performing mathematical operations such as addition and multiplication. [1 mark]
  28. June 2022, AS Paper 2, Q08.4 (1 mark): Explain why increasing the data bus width can lead to improvements in processor performance. [1 mark]
  29. June 2022, AS Paper 2, Q09.1 (1 mark): Table 1 shows the standard AQA assembly language instruction set that should be used to answer question . 1 0 9 and question 0 9 . 2 Table 1 – standard AQA asse
  30. June 2022, AS Paper 2, Q09.2 (4 marks): A computer program is required that will multiply the value stored in X by 2 if it is less than 50 and leave it unchanged if it is 50 or more. The algorithm for
  31. November 2021, Paper 2, Q06.1 (6 marks): Complete the trace table below to show the results of executing the program in Figure 4 when the initial values in registers R1 and R2 are 34 and 6 Each registe
  32. November 2021, Paper 2, Q06.2 (2 marks): The initial values for the program (its inputs) are stored in R1 and R2 and the final values stored in R0 and R1 are its outputs. By considering the inputs and
  33. November 2021, Paper 2, Q14.2 (3 marks): The control unit is an important component of a processor. Describe the role of the control unit. [3 marks]
  34. November 2021, Paper 2, Q14.3 (4 marks): One method that can be used to improve the performance of a processor is to increase the amount of cache memory. Describe: • what cache memory is • what cache m
  35. November 2020, Paper 2, Q03.4 (2 marks): The diagram in Figure 2 describes the fetch part of the Fetch-Execute cycle. Some of the names of registers have been omitted from the figure and replaced with
  36. November 2020, Paper 2, Q03.5 (2 marks): Interrupts can be generated by devices connected to the processor during the Fetch-Execute cycle. Describe the role of interrupts. [2 marks]
  37. November 2020, Paper 2, Q03.6 (2 marks): Explain why the volatile environment (the contents of registers) must be saved before an interrupt is serviced. [2 marks]
  38. November 2020, Paper 2, Q09.1 (1 mark): If the operand can be used to refer to any location in the memory, how many memory locations can the processor address? [1 mark]
  39. November 2020, Paper 2, Q09.2 (1 mark): One of the two addressing modes that the processor supports is immediate addressing. Explain what is meant by immediate addressing. [1 mark] Table 2 – Standard
  40. November 2020, Paper 2, Q09.3 (3 marks): 0 9 Figure 11 shows the format of a machine code instruction for a particular processor and one instruction in that format. Figure 11 LDR Rd, <memory ref> Load
  41. November 2020, AS Paper 2, Q06.1 (1 mark): The memory buffer register and the program counter are examples of registers. What is a register? [1 mark]
  42. November 2020, AS Paper 2, Q06.5 (8 marks): Describe four steps that a processor goes through during the fetch stage of the Fetch-Execute cycle. You must explain the purpose of each step. [8 marks]
  43. November 2020, AS Paper 2, Q07.1 (4 marks): Table 1 – standard AQA assembly language instruction set LDR Rd, <memory ref> Load the value stored in the memory location specified by <memory ref> into regist
  44. November 2020, AS Paper 2, Q07.2 (1 mark): An instruction uses immediate addressing. What is immediate addressing? [1 mark]

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