Structure and function of the processor: OCR A‑Level Computer Science questions
Every OCR A-Level Computer Science exam question on 1.1.1 Structure and function of the processor, 2021–2025, with its mark scheme and examiner’s report.
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Q1(a)
The whole paper ↗![June 2025 Paper 1, question 1(a): Charlie’s computer contains a data bus, an address bus and a control bus. State the purpose of each of these three buses. Data bus Address bus Control bus [3]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun25-01-a-qp.webp)
Q2(a)(i)
The whole paper ↗![June 2025 Paper 1, question 2(a)(i): Compare two differences between the Von Neumann architecture and the Harvard architecture. Difference 1 Difference 2 [4]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun25-02-ai-qp.webp)
Q2(a)(ii)
The whole paper ↗![June 2025 Paper 1, question 2(a)(ii): OCR Consultants is considering using pipelining. State two benefits of using pipelining. Benefit 1 Benefit 2 [2]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun25-02-aii-qp.webp)

Q1(a)
The whole paper ↗![June 2025 AS Paper 1, question 1(a): State the name of each register in the table. Register A Register B Register C Register D [4]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h04601-jun25-01-a-qp.webp)
Q1(b)(i)
The whole paper ↗![June 2025 AS Paper 1, question 1(b)(i): The number of cores [1]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h04601-jun25-01-bi-qp.webp)
Q1(b)(ii)
The whole paper ↗![June 2025 AS Paper 1, question 1(b)(ii): The clock speed [1]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h04601-jun25-01-bii-qp.webp)
Q1(a)
The whole paper ↗
Q1(b)
The whole paper ↗
Q1(c)
The whole paper ↗


Q1(a)
The whole paper ↗![June 2023 AS Paper 1, question 1(a): Describe two factors that affect the performance of the CPU. 1 2 [4]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h04601-jun23-01-a-qp.webp)
Q1(a)(i)
The whole paper ↗![June 2022 Paper 1, question 1(a)(i): Describe what is meant by the term ‘Von Neumann architecture’. [2]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun22-01-ai-qp.webp)
Q1(a)(ii)
The whole paper ↗![June 2022 Paper 1, question 1(a)(ii): Give one way that the Harvard architecture differs from the Von Neumann architecture. [1]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun22-01-aii-qp.webp)
Q1(b)
The whole paper ↗
Q1(c)(iii)
The whole paper ↗![June 2022 Paper 1, question 1(c)(iii): This program is run on a processor that allows pipelining. Define the term ‘pipelining’. [3]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun22-01-ciii-qp.webp)
Q1(c)(iv)
The whole paper ↗![June 2022 Paper 1, question 1(c)(iv): Explain one benefit to the charity of using a processor that allows pipelining. [2]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun22-01-civ-qp.webp)
Q1(d)(i)
The whole paper ↗![June 2022 Paper 1, question 1(d)(i): Describe how the accumulator is used during the Fetch-Decode-Execute cycle. [2]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun22-01-di-qp.webp)
Q1(d)(ii)
The whole paper ↗![June 2022 Paper 1, question 1(d)(ii): Describe how the program counter is used during the Fetch-Decode-Execute cycle. [2]](https://pub-e8a9dbab8e2a4d089f52b2a45e0d0b50.r2.dev/bank/h44601-jun22-01-dii-qp.webp)
All 29 questions on Structure and function of the processor, as a list
- June 2025, Paper 1, Q1(a) (3 marks): Charlie’s computer contains a data bus, an address bus and a control bus. State the purpose of each of these three buses. Data bus Address bus Control bus [3]
- June 2025, Paper 1, Q2(a)(i) (4 marks): Compare two differences between the Von Neumann architecture and the Harvard architecture. Difference 1 Difference 2 [4]
- June 2025, Paper 1, Q2(a)(ii) (2 marks): OCR Consultants is considering using pipelining. State two benefits of using pipelining. Benefit 1 Benefit 2 [2]
- June 2025, Paper 2, Q4 (9 marks): 4* A processor is being designed to use pipelining and will need to be able to process millions of instructions. For each instruction the following stages will
- June 2025, AS Paper 1, Q1(a) (4 marks): State the name of each register in the table. Register A Register B Register C Register D [4]
- June 2025, AS Paper 1, Q1(b)(i) (1 mark): The number of cores [1]
- June 2025, AS Paper 1, Q1(b)(ii) (1 mark): The clock speed [1]
- June 2024, Paper 1, Q1(a) (4 marks): Describe what happens during the fetch stage of the Fetch-Decode-Execute cycle. You should state the different registers and buses that are used in your answer.
- June 2024, Paper 1, Q1(b) (1 mark): One of the instructions that may be fetched and executed as part of this cycle is a branch instruction. State the name of the register that would be altered in
- June 2024, Paper 1, Q1(c) (3 marks): Three ways of improving the performance of a CPU are increasing the clock speed, adding more cores and using pipelining. Explain how pipelining improves the per
- June 2024, AS Paper 1, Q1 (5 marks): Here is a diagram of a computer system. Control Bus A Address Bus B D ALU RAM C CIR E +1 Control Unit CPU Identify each of the labelled components in this compu
- June 2024, AS Paper 1, Q2 (9 marks): 2* Most modern computers are designed using Von Neumann Architecture. However, in some cases Harvard Architecture may be preferred. Discuss the difference betwe
- June 2023, AS Paper 1, Q1(a) (4 marks): Describe two factors that affect the performance of the CPU. 1 2 [4]
- June 2022, Paper 1, Q1(a)(i) (2 marks): Describe what is meant by the term ‘Von Neumann architecture’. [2]
- June 2022, Paper 1, Q1(a)(ii) (1 mark): Give one way that the Harvard architecture differs from the Von Neumann architecture. [1]
- June 2022, Paper 1, Q1(b) (2 marks): The charity is concerned that the performance of the computer is not sufficient and wishes to replace the processor. Give two features of a replacement processo
- June 2022, Paper 1, Q1(c)(iii) (3 marks): This program is run on a processor that allows pipelining. Define the term ‘pipelining’. [3]
- June 2022, Paper 1, Q1(c)(iv) (2 marks): Explain one benefit to the charity of using a processor that allows pipelining. [2]
- June 2022, Paper 1, Q1(d)(i) (2 marks): Describe how the accumulator is used during the Fetch-Decode-Execute cycle. [2]
- June 2022, Paper 1, Q1(d)(ii) (2 marks): Describe how the program counter is used during the Fetch-Decode-Execute cycle. [2]
- June 2022, Paper 1, Q1(d)(iii) (3 marks): State the name of three other registers that are used during the Fetch-Decode-Execute cycle. 1 2 3 [3]
- June 2022, AS Paper 1, Q1(d)(i) (2 marks): Describe the Harvard architecture. [2]
- June 2022, AS Paper 1, Q1(d)(ii) (2 marks): Arnold has a smart washing machine. Explain why the Harvard architecture is suitable for a device like this. [2]
- November 2021, Paper 1, Q1(a)(i) (2 marks): State two factors that affect the performance of a CPU. 1 2 [2]
- November 2021, Paper 1, Q1(b) (3 marks): The CPU uses pipelining to improve efficiency. Explain what is meant by the term ‘pipelining’. [3]
- November 2021, Paper 1, Q6(a)(i) (2 marks): State what is meant by the term ‘register’. [2]
- November 2021, Paper 1, Q6(a)(ii) (2 marks): Explain how the accumulator is used when the line BRP pos is executed. [2]
- November 2021, Paper 2, Q6(a) (4 marks): The processor’s pipeline consists of the following stages: • Fetching the instruction from memory • Decoding the instruction • Executing the instruction. Instru
- November 2021, Paper 2, Q6(b) (2 marks): Explain why pipelining can improve the performance of the processor. [2]
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