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The CPU and the fetch-decode-execute cycle: Edexcel GCSE Computer Science questions

Every Edexcel GCSE Computer Science exam question on 3.1.1 The CPU and the fetch-decode-execute cycle, 2022–2025, with its mark scheme and examiner’s report.

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210 questions

  1. Q2(f)

    June 2025 · Paper 1

    4 marks3.1.1 The CPU and the fetch-decode-execute cycle
    The whole paper ↗

  2. Q4(e)

    June 2024 · Paper 1

    3 marks3.1.1 The CPU and the fetch-decode-execute cycle
    The whole paper ↗

  3. Q1(a)(i)

    June 2023 · Paper 1

    3 marks3.1.1 The CPU and the fetch-decode-execute cycle
    The whole paper ↗

  4. Q1(a)(ii)

    June 2023 · Paper 1

    1 mark3.1.1 The CPU and the fetch-decode-execute cycle
    The whole paper ↗
    Your answer

  5. Q2(b)

    June 2022 · Paper 1

    2 marks3.1.1 The CPU and the fetch-decode-execute cycle
    The whole paper ↗

  6. Q4(c)

    Specimen · Paper 1

    4 marks3.1.1 The CPU and the fetch-decode-execute cycle
    The whole paper ↗
All 6 questions on The CPU and the fetch-decode-execute cycle, as a list
  1. June 2025, Paper 1, Q2(f) (4 marks): Here is a diagram of a central processing unit. C Control bus Registers A 1011 1111 0011 0011 Data bus 0111 1011 D 1100 0111 0111 1101 ALU 0000 0001 B Complete
  2. June 2024, Paper 1, Q4(e) (3 marks): The components of a computer carry out the fetch‑decode‑execute cycle. Complete the diagram with: the names of two buses • • a directional connection from the c
  3. June 2023, Paper 1, Q1(a)(i) (3 marks): Complete the table with the correct bus for each role. (3) Bus Role Carries a read signal to main memory. Carries the memory location of a piece of data. Carrie
  4. June 2023, Paper 1, Q1(a)(ii) (1 mark): Identify the component inside the CPU that stores data. (1) A Arithmetic logic unit B Clock C Main memory D Register
  5. June 2022, Paper 1, Q2(b) (2 marks): State the two items held in RAM according to the von Neumann architecture. (2) 1 2
  6. Specimen, Paper 1, Q4(c) (4 marks): Describe the role of the control unit, the control bus, the data bus and the address bus when fetching an instruction from memory. (4)

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